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Samsung plans to more than double production of its HBM4 chips in 2027, according to industry sources consulted by Seoul Economic Daily. To achieve this, the South Korean company needs 2.5 times more glass carriers, a glass support that holds the DRAM wafer while it’s thinned for stacking, and which today is one of the least visible bottlenecks in the entire AI memory supply chain.
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TL;DR
- Samsung plans to more than double HBM4 and HBM4E production in 2027 compared to 2026, according to industry sources.
- Demand for glass carriers will rise 2.5 times: from 20,000 monthly sheets in 2026 to 50,000 in 2027.
- Just a year ago, in 2025, the requirement was only 10,000 sheets per month.
- In February 2026, Samsung began mass production shipments of HBM4 with 10nm-class 1c DRAM and a 4nm base die.
- By May 2026, it had already delivered 12-layer HBM4E samples to customers, including Nvidia.
- Total HBM production volume would grow by nearly 40%, from 180,000 to 250,000 wafers per month.
- That shift also shows up in the product mix: it will rise from ~40% of shipments in 2026 to ~80% in 2027.
- Industry analysts consider it highly likely that HBM4 and HBM4E production will at least double.
What happened
Samsung Electronics (KRX: 005930) plans to raise the volume of outsourced glass carrier cleaning from 20,000 monthly sheets in 2026 to 50,000 sheets per month in 2027, according to industry sources cited on September 20, 2026. This matters because the glass carrier is a consumable that accompanies every HBM4 and HBM4E wafer during the thinning process.
An industry official summarized the move this way: “As Samsung expands HBM production, it appears to be placing HBM4, a high-value product, at the center”. The quote, reported by the same South Korean outlet, reflects a product decision: concentrating the plant on the most profitable line rather than splitting capacity between generations.
The growth isn’t linear. Analysts themselves warn that glass carriers are reused after each cleaning, and that consumption varies depending on the process loading method and the yield of each line. Even with those nuances, they calculate that a 2.5x jump in the related volume makes it highly likely that HBM4 and HBM4E production will at least double compared to 2026.
Context and history: from 10,000 to 50,000 glass sheets per month
Just a year ago, in 2025, Samsung needed about 10,000 glass carrier sheets per month to sustain its HBM production. In 2026 that number doubled to 20,000. For 2027 the projection is 50,000, a curve growing faster than the very demand for AI GPUs that consume this memory.
| Year | Monthly glass carrier volume | Change |
|---|---|---|
| 2025 | 10,000 sheets | Baseline |
| 2026 | 20,000 sheets | 2x vs. 2025 |
| 2027 (projected) | 50,000 sheets | 2.5x vs. 2026 |
The reason behind that curve is physical, not just commercial. The more DRAM layers an HBM module stacks, the thinner each individual wafer needs to be so the final package doesn’t exceed the maximum thickness allowed by the standard. And a thinner wafer bends and breaks more easily during the process, so it needs more support, not less.
Technical details: what a glass carrier actually does
A glass carrier is a glass plate temporarily bonded to the underside of the DRAM wafer. It serves a single function: preventing the wafer from warping or cracking while a grinder wears it down to just a few dozen microns thick, and while the through-silicon vias (TSVs) that will connect each stacked layer to the next are drilled.
The products Samsung is scaling up (sixth-generation HBM4 and seventh-generation HBM4E) target stacks of 12 layers or more. The more layers, the greater the importance of controlling warpage: the curvature a thin wafer experiences under thermal or mechanical stress. Without a high-flatness glass carrier, that curvature ruins TSV alignment between layers.
flowchart TD
A["DRAM wafer"] --> B["Glass carrier attachment"]
B --> C["Thinning and TSV drilling"]
C --> D["Glass carrier removal"]
D --> E["Stacking up to 12 layers"]
E --> F[("HBM4 / HBM4E module")]That cycle repeats for every wafer in the batch. The carrier is cleaned and reused when possible, which explains why Samsung measures growth in outsourced cleaning volume rather than just new units.
| Generation | Process | Production status |
|---|---|---|
| HBM4 (6th generation) | 10nm-class 1c DRAM, 4nm-process base die | Mass production shipments since February 2026 |
| HBM4E (7th generation) | 12-layer stack | Samples delivered to customers, including Nvidia, since May 2026 |
How to check how much HBM your AI hardware has
If you work with inference or training infrastructure, HBM4 production matters to you indirectly: it’s the memory mounted on every modern AI accelerator, and its availability affects the price and delivery time of complete GPUs. Before assuming bottlenecks, the first step is confirming what memory your hardware actually carries.
On a node with Nvidia GPUs, nvidia-smi reports total memory capacity per device:
nvidia-smi --query-gpu=name,memory.total,memory.used --format=csvThat command returns the accelerator’s name along with its total and used memory in megabytes, without relying on any additional driver.
For a more detailed check (for example, if you manage a cluster and need to decide where to place a model with high memory bandwidth requirements), pynvml lets you query status per process:
import pynvml
pynvml.nvmlInit()
handle = pynvml.nvmlDeviceGetHandleByIndex(0)
info = pynvml.nvmlDeviceGetMemoryInfo(handle)
print(f"Total memory: {info.total / 1024**3:.1f} GB")
print(f"Memory in use: {info.used / 1024**3:.1f} GB")
print(f"Free memory: {info.free / 1024**3:.1f} GB")
pynvml.nvmlShutdown()This script prints total, used, and free memory per GPU in gigabytes. It’s the same data shown by nvidia-smi, but scriptable inside a monitoring pipeline or a job scheduler that needs to decide which node a model fits on based on its memory footprint.
💡 Tip: memory capacity per GPU says nothing about bandwidth. For that, it’s worth checking the accelerator’s datasheet or running a bandwidth benchmark like CUDA Samples’ bandwidthTest.
Impact and analysis: what the HBM4 jump means for AI
The shift in product mix is the most revealing part of the report. This year, HBM4 accounts for about 40% of Samsung’s shipments; for 2027 the projection rises to about 80%, as mass production of HBM4E gains volume. At the same time, total HBM production volume (measured in monthly input wafers) would grow by nearly 40%, from 180,000 to 250,000 wafers per month.
Those two numbers together explain the strategy. Samsung isn’t just making more HBM: it’s making more HBM4 specifically, the product that the next generations of AI accelerators, including the ones Nvidia builds, need to sustain the memory bandwidth the largest models demand.
Competitors aren’t standing still. SK Hynix and Micron are running the same layer-count and customer race, though the Seoul Economic Daily report focuses on Samsung’s internal plans and doesn’t compare volumes across manufacturers. What it does make clear is that the physical bottleneck (how many wafers can be thinned and stacked per month) matters as much as chip design.
⚠️ Note: an increase in glass carrier demand doesn’t automatically translate into double the usable chips: each line’s yield and the process loading method also determine how much memory ultimately ships.
What’s next
The timeline industry sources are working with points to the jump from 20,000 to 50,000 monthly glass carrier sheets happening during 2027, in parallel with increased HBM4E production. If those numbers hold, the market should start noticing greater HBM4 availability toward the second half of that year, right as the next AI accelerators that depend on that memory enter production.
Open questions remain that the report doesn’t answer: how much of that increase goes to customers outside Nvidia, whether SK Hynix or Micron announce comparable capacity plans, and whether the thinning process itself becomes a harder limit to work around than glass carrier availability itself.
📖 Summary on Telegram: View summary
If you follow the memory supply chain closely, it’s worth reading the full Seoul Economic Daily report with the industry source figures before other outlets republish it with less detail.
Frequently Asked Questions
What is a glass carrier and why is it so important for HBM4?
It’s a glass plate temporarily bonded to a DRAM wafer to hold it in place while it’s thinned and its TSVs are drilled. Without that support, the wafer would warp or break before it could be stacked.
How much will Samsung’s HBM4 production grow in 2027?
According to industry sources, HBM4 and HBM4E production would grow at least twofold compared to 2026, driven by a 2.5-times increase in glass carrier volume.
What’s the difference between HBM4 and HBM4E?
HBM4 is the sixth generation of the standard and has been in mass production since February 2026 with 10nm-class DRAM. HBM4E is the seventh generation, with 12-layer stacks, and as of May 2026 was in the customer sampling phase.
Who is receiving Samsung’s HBM4E samples?
The report mentions Nvidia among the customers that received 12-layer HBM4E samples in May 2026, though it doesn’t rule out other unnamed buyers.
Does this announcement affect AI GPU pricing?
The report doesn’t include pricing data. What it does establish is an increase in production capacity, which tends to ease supply pressure on HBM memory, one of the most expensive components in an AI accelerator.
References
- Seoul Economic Daily: original report with industry source figures on Samsung’s HBM4 and glass carrier production.
- Wikipedia: High Bandwidth Memory: technical context on the HBM standard’s generations and evolution.
- Samsung Newsroom Global: official statements from Samsung Electronics on its memory products.
- JEDEC: the organization that standardizes HBM memory specifications, including the HBM4 family.
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