Industrial RISC-V: what gap does ERICI’s open stack target?

⏱️ Reading time: 13 min

ERICI arrived this week with a precise goal: get a board with the RISC-V RVA23 profile to boot like a real industrial computer, running Linux and a real-time system simultaneously on the same chip. RVA23 silicon has already been on sale since 2026: eight 64-bit cores, hypervisor extension, IOMMU. But no manufacturer yet ships the software stack that turns that silicon into an industrial RISC-V computer ready to run a factory for a decade.

📑 En este artículo

1. TL;DR
2. What is industrial RISC-V?
3. Why ERICI’s open stack matters
   1. An ISA with no owner
   2. RVA23, the first common floor
   3. The silicon is already on sale
   4. One box instead of two
4. How it works: the seven layers of the reference stack
   1. Boot sequence
5. How to test it: emulating RVA23 with QEMU
6. Industrial RISC-V against plant requirements: AIBOX-K3 and Jupiter2
7. Real use cases on the plant floor
8. Common mistakes when evaluating an RVA23 board for production
9. Going deeper: the partitioning hypervisor and the IOMMU
10. Frequently Asked Questions
    1. What is industrial RISC-V, and how does it differ from a consumer RISC-V SoC?
    2. What does the RVA23 profile solve compared to previous RISC-V versions?
    3. Can I buy a board with the RVA23 profile today?
    4. What does the gRouvr partitioning hypervisor do?
    5. Does ERICI certify or sell hardware?
    6. Does the ERICI reference stack replace Arm and x86 in industry?
11. References

European RISC-V Industrial Computing Initiative, ERICI’s full name, doesn’t sell hardware. It defines an open reference stack (firmware, partitioning hypervisor, RTOS, and general-purpose operating system) and verifies it layer by layer on real RVA23 boards. A board that boots that full stack is declared ERICI compatible.

TL;DR

• ERICI defines a seven-layer industrial RISC-V stack, from firmware to Linux, verified on real RVA23 hardware.
• The RVA23 profile, ratified in October 2024, makes the hypervisor and vector extensions mandatory.
• A partitioning hypervisor like gRouvr runs real-time control and Linux on the same chip, isolated from each other.
• Boards like the Firefly AIBOX-K3 and the Milk-V Jupiter2 already carry the SpacemiT K3 SoC with eight RVA23 cores.
• Neither one yet certifies industrial temperature range or a partitioned stack: that’s the gap ERICI is targeting.

What is industrial RISC-V?

Industrial RISC-V is the application of the open RISC-V instruction set to computers meant for plants, machinery, and process control: equipment that must run for a decade or more, isolate real-time control from the rest of the system, and not depend on a single CPU manufacturer’s license.

RISC-V is an instruction set (ISA) born in 2010 at the University of California, Berkeley. Unlike x86, owned by Intel and AMD, or Arm, licensed by Arm Holdings to each manufacturer, nobody owns RISC-V. It’s governed by RISC-V International, a nonprofit foundation based in Switzerland since 2020, and any company can implement it without paying royalties for the base design.

The timeline explains why a project like ERICI is only appearing now:

• 2010: RISC-V is born at UC Berkeley.
• 2015: the RISC-V Foundation is founded.
• 2020: it becomes RISC-V International, based in Switzerland.
• 2021: the hypervisor and vector extensions are ratified.
• 2024: the RVA23 profile is ratified.
• 2026: the first RVA23 boards arrive, and ERICI is born.

Why ERICI’s open stack matters

An industrial controller doesn’t get swapped out every two years like a phone. It lives fifteen years soldered inside an electrical cabinet, and during that time it depends on someone continuing to manufacture the chip and sign the firmware updates. That’s why the openness of the instruction set isn’t an ideological preference: it’s a condition for long-term survival.

An ISA with no owner

With x86, two companies decide the future of the instruction set. With Arm, Arm Holdings sets the licensing terms for every design, from a microcontroller to a server. With the open RISC-V stack, no single company or country controls the specification: whoever wants to can implement it, and a manufacturer can stop selling without the standard disappearing along with it.

RVA23, the first common floor

The RVA23 profile, ratified in October 2024 by RISC-V International, solves the problem that held RISC-V back in industry for a decade: fragmentation of optional extensions. RVA23 makes the hypervisor extension and the vector extension mandatory in any chip that wants to call itself compatible. Software can now assume both pieces are present in any SoC carrying that label, instead of testing combination by combination.

The silicon is already on sale

The first boards with RVA23 SoCs hit the market in 2026, with eight 64-bit cores and an IOMMU, as described by ERICI. A developer can buy them today. The bottleneck is no longer the chip: it’s everything missing around the chip for it to be a complete industrial RISC-V computer.

One box instead of two

Today a plant typically uses two machines: a dedicated PLC or RTOS for real-time control, and a separate industrial PC for the operator interface. A partitioning hypervisor lets both roles run, isolated from each other, on a single RVA23 SoC. This isn’t just hardware savings: fewer boxes mean fewer cables, fewer failure points, and less surface area to certify.

flowchart LR
    subgraph Today
    X1["Box 1: dedicated PLC or RTOS"]
    X2["Box 2: industrial PC with Linux"]
    end
    subgraph ERICI
    Y1["One RVA23 SoC"]
    Y2["gRouvr partitions CPU and memory"]
    Y1 --> Y2
    Y2 --> Y3["QSOE partition: real time"]
    Y2 --> Y4["Linux partition: operator"]
    end

How it works: the seven layers of the reference stack

ERICI doesn’t invent new software at every layer. It defines the interface between each pair of layers and verifies that the whole set boots together on real hardware. The reference components are developed by QSOE Systems; Linux is contributed by its own community.

• Hardware: the RVA23 SoC, the SpacemiT K3 on current boards, with its cores, memory, devices, and IOMMU.
• Firmware, HFI BIOS: based on U-Boot, it runs the POST and exposes a BIOS-style configuration menu for industrial boards. Interface upward: the RVA23 profile.
• Loader, mr-bml: a boot loader with a menu, where the operator chooses which system to start. Interface: a UEFI application.
• Partitioning, gRouvr: the hypervisor that distributes CPU, memory, devices, and IOMMU among partitions. Interface upward: kernel plus initrd, same as Linux.
• Real-time partition, QSOE: a QNX-style environment, with /N on the proprietary Skimmer microkernel and /L on seL4, both sharing the same userspace. /L boots with Multiboot3.
• Operator partition, Linux: the graphical interface, the HMI, and network connectivity, on a general-purpose operating system.

flowchart TD
    A["RVA23 SoC (cores, IOMMU)"] --> B["HFI BIOS: boot firmware"]
    B --> C["mr-bml: system selector"]
    C --> D["gRouvr: partitioning hypervisor"]
    D --> E["Real-time partition: QSOE"]
    D --> F["Operator partition: Linux"]

Boot sequence

Order matters. The SoC powers on and the HFI BIOS runs the POST. It hands control to mr-bml, which presents the boot menu. mr-bml loads gRouvr, which partitions CPU, memory, and IOMMU, and only then do the real-time partition and the Linux partition boot in parallel.

sequenceDiagram
    participant S as RVA23 SoC
    participant F as HFI BIOS
    participant L as mr-bml
    participant H as gRouvr
    S->>F: POST and memory initialization
    F->>L: hands control via UEFI
    L->>H: loads the partitioning hypervisor
    H->>H: distributes CPU, memory, and IOMMU
    Note over H: QSOE and Linux boot in parallel

How to test it: emulating RVA23 with QEMU

Nobody needs to buy a board to try RISC-V with the hypervisor extension. QEMU has emulated the H extension for several versions now, and it’s the cheapest way to see how Linux boots on a RISC-V core with that extension active.

On Debian or Ubuntu, install the emulator and the boot firmware:

sudo apt install qemu-system-misc opensbi u-boot-qemu

This installs qemu-system-riscv64, the OpenSBI firmware (the RISC-V equivalent of a minimal BIOS), and a U-Boot build for QEMU’s virt virtual machine.

Boot a virtual machine with the hypervisor extension enabled:

qemu-system-riscv64 -machine virt -cpu rv64,h=true -smp 2 -m 2G -nographic \n  -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf \n  -kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf

The h=true flag activates the hypervisor extension on the virtual core QEMU emulates, the same extension RVA23 makes mandatory on real silicon. After a few seconds you should see the U-Boot prompt in the terminal.

Once a Linux boots on that virtual machine, confirm the kernel sees the extension by checking the ISA string it exposes:

grep isa /proc/cpuinfo

The output includes the letter h within the extension string, for example a line similar to isa : rv64imafdch_zicsr_zifencei_zba_zbb. If the h doesn’t show up, the kernel you compiled doesn’t include hypervisor support, or QEMU isn’t emulating it in that build.

On macOS and Windows the same qemu-system-riscv64 package is available via Homebrew or the official QEMU installer, with the same flags.

📌 Note: this emulates RVA23’s hypervisor extension, not ERICI’s gRouvr partitioning hypervisor, which isn’t publicly downloadable software yet.

Industrial RISC-V against plant requirements: AIBOX-K3 and Jupiter2

ERICI points to two boards already available as a starting point: the Firefly AIBOX-K3, from T-Chip Intelligent Technology, and the Milk-V Jupiter2. Both carry the same SoC, the SpacemiT K3, with eight X100 cores clocked up to 2.4 GHz and the RVA23 profile. Neither is yet a complete industrial computer.

Specifications published by the manufacturers in October 2026, as reported by ERICI. The partitioned stack was indeed demonstrated, but on a different board, the SpacemiT K3 PicoITX, not on these two products.

Real use cases on the plant floor

Consider a robotic cell: a control loop moving an arm over EtherCAT needs deterministic cycles of a few milliseconds, while the operator panel needs networking, a browser for the HMI, and increasingly a vision model running inference. Today that requires two boxes. With a partitioning hypervisor, the QSOE partition handles the EtherCAT loop and the Linux partition runs the HMI and the vision model, on the same RVA23 SoC.

The Firefly AIBOX-K3 is sold as an edge mini PC: it fits visual inspection scenarios or protocol gateways, where today it only runs Linux. The leap ERICI proposes is that, once the partitioned stack reaches boards like this one, the same chip could also sustain the real-time control loop without depending on an external PLC.

Common mistakes when evaluating an RVA23 board for production

Confusing “has hypervisor extension” with “has a certified partitioned stack” is the costliest mistake. The gRouvr and QSOE software doesn’t yet run on the AIBOX-K3 or the Jupiter2; it was only demonstrated on a different board.

“Not stated” on a datasheet doesn’t mean “not supported”: it means the manufacturer didn’t publish it. It’s worth requesting it in writing before designing a full cabinet around that board.

Assuming that an edge mini PC’s temperature range, -20 to 60°C on the AIBOX-K3, is enough for an uncooled electrical cabinet is another typical risk: many plants require -40 to 85°C.

Treating RVA23 as a guarantee of total binary compatibility is also incorrect. The profile sets the floor of mandatory extensions, but the vector and AI extensions keep evolving beyond that baseline.

⚠️ Watch out: neither board in this article declares industrial EMC certification or guaranteed ten-year availability; they’re examples of available RVA23 silicon, not finished industrial products.

Going deeper: the partitioning hypervisor and the IOMMU

A partitioning hypervisor like gRouvr doesn’t do the same job as a traditional virtualization hypervisor. Instead of creating generic virtual machines, it fixedly assigns CPU cores, memory ranges, and entire devices to each partition. The IOMMU (the input/output memory management unit) is the piece that enforces that allocation at the hardware level: it prevents a device controlled by one partition from writing, via DMA, into another partition’s memory. A software-only hypervisor can’t provide that guarantee without an IOMMU.

Within the real-time partition, QSOE offers two variants sharing the same userspace: /N runs on the proprietary Skimmer microkernel, in the style of classic QNX systems; /L runs on seL4, the formally verified microkernel, and boots with Multiboot3 instead of devicetree plus kernel plus initrd. That dual option allows choosing between an industry-proven design or one with mathematical isolation guarantees, without rewriting the application.

mr-bml closes the loop: it works as a UEFI application with a menu, similar in spirit to GRUB, but designed so a plant operator can choose between installed systems without touching a line of configuration.

Your next step: install qemu-system-riscv64 and boot the virtual machine with -cpu rv64,h=true to see with your own eyes the hypervisor flag that RVA23 makes mandatory on real silicon.

Frequently Asked Questions

What is industrial RISC-V, and how does it differ from a consumer RISC-V SoC?

It’s the same instruction set architecture applied to equipment that must run for ten years or more, with real-time partitioning, wide temperature ranges, and EMC certification, requirements a consumer SoC doesn’t need to meet.

What does the RVA23 profile solve compared to previous RISC-V versions?

RVA23, ratified in October 2024, makes the hypervisor and vector extensions mandatory in every compatible chip, eliminating the fragmentation of optional extensions that held back software.

Can I buy a board with the RVA23 profile today?

Yes. The Firefly AIBOX-K3 and the Milk-V Jupiter2, both with the eight-core SpacemiT K3 SoC, have already been available on the market since 2026.

What does the gRouvr partitioning hypervisor do?

It fixedly distributes the SoC’s CPU cores, memory, and devices among isolated partitions, using the IOMMU to prevent cross-partition memory access.

Does ERICI certify or sell hardware?

No. It defines a reference stack and verifies that it boots completely on real RVA23 hardware; the “ERICI compatible” label is earned by a board that achieves that boot, not a formal industrial certification seal.

Does the ERICI reference stack replace Arm and x86 in industry?

Not yet. It solves the software gap on RVA23 silicon, but it still lacks the EMC certifications, extended temperature ranges, and guaranteed long-term availability that x86 and Arm already offer in mature industrial products.

References

• ERICI, European RISC-V Industrial Computing Initiative: the reference stack, the layer diagram, and the board specifications cited in this article.
• RISC-V International: official specification of the RVA23 profile and governance of the instruction set.
• Wikipedia: RISC-V: history of the project since its origin at UC Berkeley in 2010.
• QEMU: documentation for the emulator used in the section on testing the hypervisor extension.

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Featured image: Foto de Yogesh Phuyal en Unsplash