⏱️ Lectura: 13 min
The CH32V003, a RISC-V microcontroller costing just 10 cents, is at the center of a response an embedded engineer from Trinidad and Tobago published on August 16, 2026, against one of the harshest attacks the architecture has received in years.
📑 En este artículo
The original article, by Dmitry Grinberg, hit the front page of Hacker News and sparked a long discussion on Lobsters. The reply, published on rvembedded.com, does not defend every decision made by the RISC-V committee: it attacks a different point, one that almost no one addressed in those threads.
TL;DR
- Dmitry Grinberg published “RISC-V: They Should Have Known Better” and it hit the front page of Hacker News.
- An embedded engineer from Trinidad and Tobago responded on August 16, 2026, on rvembedded.com.
- The CH32V003 is an RV32EC RISC-V microcontroller costing about 10 cents, with 2 KB of RAM and 16 KB of flash.
- Grinberg deduced the requirements for a cheap core from scratch and arrived exactly at RV32EC, the one the CH32V003 uses.
- Grinberg himself wrote that he is “100% sure” RISC-V will dominate the disposable microcontroller segment.
- The author paid between US$60 and US$200 in shipping for one-dollar chips, without the free shipping typical in the US and Europe.
- He used the CH32V003 in two real products: a container monitor with a ToF sensor and an agricultural gate controller.
- The debate remains open on Lobsters with no possible technical resolution: it’s a discussion about access, not just about encoding.
What happened
Dmitry Grinberg published “RISC-V: They Should Have Known Better,” a lengthy essay about the instruction encoding decisions that, in his view, make RISC-V a poorly designed architecture for both high-performance processors and cheap microcontrollers. The piece hit the front page of Hacker News and generated a long thread on Lobsters, two of the forums where hardware design is discussed most among software and firmware engineers.
The response came three days later, on August 16, 2026, when an engineer working from Trinidad and Tobago published his reply on rvembedded.com. His starting point isn’t technical: it’s geographic. Before offering an opinion on instruction encoding, he describes what it costs to get hold of a one-dollar chip when you live outside the United States or Europe.
Context and history
RISC-V is an open, royalty-free instruction set architecture (ISA), originally developed at UC Berkeley and now governed by RISC-V International. Unlike ARM or x86, any manufacturer can implement the core without paying a license fee, which has drastically cut the cost of the simplest microcontrollers.
The chip the article discusses is the CH32V003, made by the Chinese company WCH, which implements RV32EC, a reduced 32-bit RISC-V variant with the compressed instructions extension. The author of the reply didn’t pick it at random: he’s used it in production for over a year. In 2025 he published a video titled “Goodbye STM32 ARM, Meet the CH32 RISC-V Chips That Replaced It!” documenting his full migration from ARM to this chip family.
His central argument doesn’t attack the elegance of the instruction encoding, which he acknowledges is imperfect (the offsets on compressed store instructions strike him as odd, and Zicsr should come included by default instead of being a separate extension you have to remember to request). It attacks the premise that ISA design is the only thing that matters. He recounts paying between US$60 and US$200 in shipping for orders of one-dollar chips, while buying from Digikey or Mouser with free shipping is the norm for a developer in the United States or Europe. A board manufacturing company that had contacted him about a possible sponsorship pulled the offer as soon as it learned where he was shipping from.
Technical details of the CH32V003 RISC-V microcontroller
Before the complaints about encoding, Grinberg does a different exercise: he asks what a cheap microcontroller core is actually for. His answer is that it lives inside a larger chip, flipping registers and configuring hardware blocks (his examples are an MP3 player, an SD card reader, a USB drive). The real work is done by the custom silicon around the core, not by the core itself.
From there he derives the requirements: low interrupt latency, small silicon area, and good code density, because code lives in ROM or SRAM and both are expensive per byte. No hardware multiplier or divider, because there’s almost no heavy arithmetic. No privilege separation, because it never runs anything untrusted.
And then he writes the line himself: “But,” you might say, “you just described RV32IC (or RV32EC)!” Further on, bluntly, he admits: “I’m 100% sure RISC-V is going to own the cheap, disposable microcontroller segment, eventually.” The most-cited critic of the month deduced from scratch, with pencil and paper, the instruction set already implemented by a ten-cent chip, and then spent the rest of the article annoyed that such a chip exists.
The CH32V003 itself has minimal specs: 16 general-purpose registers (the “E” in RV32E, versus the 32 registers of the standard RV32I variant), 2 KB of SRAM, 16 KB of flash, no multiplier, no divider, and machine mode only, with no additional privilege levels. It’s literally the core Grinberg described as ideal before criticizing its existence.
flowchart TD
A["Cheap core inside a larger chip"] --> B["Low interrupt latency"]
A --> C["Small silicon area"]
A --> D["Good code density"]
A --> E["No multiplier or divider"]
A --> F["No privilege separation"]
B --> G["RV32EC"]
C --> G
D --> G
E --> G
F --> G| Option | When to use it | Advantage | Limitation |
|---|---|---|---|
| CH32V003 (RISC-V RV32EC) | High-volume projects where unit cost drives the design | Costs around 10 cents and uses an open ISA | No hardware multiplier or divider, machine mode only |
| STM32C0 (ARM Cortex-M0+) | When ARM code or libraries already exist and aren’t worth porting | Mature HAL ecosystem and debugging with standard ARM tools | Subject to the same import logistics as any other ARM chip |
| ATtiny402 (8-bit AVR) | Simple projects that don’t need 32-bit arithmetic | avr-gcc toolchain proven over decades | Less dense code than compressed RISC-V in complex logic |
💭 Key point: Grinberg deduced the ideal core for a cheap microcontroller from first principles and arrived exactly at RV32EC. His frustration isn’t with the engineering, it’s that the result feels like coincidence to him, not merit.
How to try a CH32V003 yourself
The chip is available on low-cost development boards, and the toolchain to program it is open. The most widely used project is ch32v003fun, maintained by hardware engineer Charles Lohr, which exposes the chip’s registers without a heavy HAL layer.
Installation on Linux (Debian/Ubuntu):
sudo apt install git make gcc
git clone https://github.com/cnlohr/ch32v003fun.git
cd ch32v003fun/ch32v003fun
make flashInstallation on macOS (with Homebrew):
brew install git make
git clone https://github.com/cnlohr/ch32v003fun.git
cd ch32v003fun/ch32v003fun
make flashInstallation on Windows (via WSL2, the most stable path since the RISC-V toolchain is designed for Linux):
wsl --install
wsl
sudo apt install git make gcc
git clone https://github.com/cnlohr/ch32v003fun.git
cd ch32v003fun/ch32v003fun
make flashThe repository downloads the RISC-V cross-compiler the first time you run make. The make flash command compiles the example and flashes it to the chip through a WCH-LinkE programmer connected via the SWIO pin.
The minimal example turns an LED on and off by writing directly to the GPIO port registers, with no intermediate abstraction layer:
#include "ch32v003fun.h"
int main() {
SystemInit();
RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
GPIOC->CFGLR &= ~(0xf << (4 * 4));
GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4);
while (1) {
GPIOC->BSHR = (1 << 4);
Delay_Ms(500);
GPIOC->BSHR = (1 << (4 + 16));
Delay_Ms(500);
}
}This code configures pin PC4 as a push-pull output and toggles it every 500 milliseconds. It’s the equivalent of “hello world” for any microcontroller.
A more realistic example, inspired by the trash container monitor the reply’s own author put into production, reads a sensor via ADC and triggers a relay when it crosses a threshold:
#include "ch32v003fun.h"
#define UMBRAL_SENSOR 600
int main() {
SystemInit();
RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_ADC1;
ADC1->RSQR3 = 0;
ADC1->CTLR2 |= ADC_ADON;
Delay_Ms(1);
ADC1->CTLR2 |= ADC_ADON;
while (1) {
ADC1->CTLR2 |= ADC_SWSTART;
while (!(ADC1->STATR & ADC_EOC));
uint16_t muestra = ADC1->RDATAR;
if (muestra > UMBRAL_SENSOR) {
GPIOC->BSHR = (1 << 4);
} else {
GPIOC->BSHR = (1 << (4 + 16));
}
}
}The double ADC_ADON isn’t a copy-paste error: in the CH32V003 family, the second edge of that signal triggers the converter’s internal calibration before the first reading.
To confirm the binary was actually compiled for the reduced core and not for a variant with a multiplier or divider, the readelf command shows the architecture string embedded in the ELF:
riscv32-unknown-elf-readelf -A firmware.elf | grep archIf the Makefile correctly targets the chip, the output should show rv32ec as the architecture string, not rv32imc or any variant with the multiplication “M” extension.
⚠️ Heads up: without a hardware multiplier or divider, any arithmetic operation other than addition or bit shifting is resolved in software. For digital filters, cryptography, or signal processing, the CH32V003 isn’t the right choice: a core with the M extension is better suited there.
Impact and analysis
The underlying disagreement isn’t about whether the CH32V003 is a good chip. It’s about whether Grinberg’s argument (that the needs of a high-performance processor are diametrically opposed to those of a cheap core, and that therefore no single ISA can serve both extremes well) holds up on its own terms. The reply’s author answers with what’s on his own desk: the same RISC-V standard covers everything from the ten-cent CH32V003 to application cores with an MMU and double-precision multiplication, with extensions that each implementation enables or ignores as needed.
That’s ultimately RISC-V’s modular design: a mandatory integer base and dozens of optional extensions (M for multiplication, C for compressed instructions, A for atomics, F and D for floating point) that a manufacturer combines depending on the market. Grinberg sees it as a source of fragmentation. The author from Trinidad and Tobago sees it as the reason a single tooling ecosystem can compile for both the CH32V003 and a much larger application core.
The reply’s strongest argument, however, isn’t architectural: it’s about access. For a student in Nigeria, Bangladesh, or the Caribbean, the difference between a ten-cent chip and a one-dollar chip isn’t rounding error, it’s the difference between thirty students in a course each having their own chip or thirty students watching a single demo board, if one even shows up. The elegance of instruction encoding is a luxury you get to debate once the hardware is already on the desk. Whether the hardware reaches the desk at all is the prior question, and none of the complaints about compressed offsets answer it.
The author also mentions a book of his own, currently about 80% finished, dedicated exclusively to documenting every quirk of the CH32V003 that a new developer ends up banging their head against: the absence of Zicsr by default, the odd offsets on compressed store instructions, and other encoding decisions that Grinberg also flags in his article. On that point, both agree: the ISA has real rough edges. Where they differ is on whether those rough edges invalidate the whole project.
What’s next
The discussion remains open on Lobsters and in the comments of both articles, with no possible technical resolution: at its core, it’s a disagreement about which problem RISC-V is trying to solve first. Meanwhile, the CH32V003 and similar chips in the CH32 family, made by WCH, keep showing up in publicly documented hobbyist projects, like the whistle-activated switch the reply’s own author built and showed off in a video.
In the short term, the debate will most likely not change the ISA’s design (RISC-V International has already locked in the base extensions), but it may well influence how computer architecture is taught at universities with limited budgets, where cost per student is already, for many programs, the deciding factor between teaching the course with real hardware or with simulators alone.
📖 Summary on Telegram: View summary
Try it yourself: clone ch32v003fun and run make flash on a CH32V003 board that costs a few dollars to see the blink running within minutes.
Frequently Asked Questions
What is the CH32V003?
It’s a 32-bit microcontroller made by the Chinese company WCH that implements RV32EC, a reduced RISC-V variant with compressed instructions. It costs around 10 cents per unit at volume.
What does RV32EC mean?
RV32 indicates a 32-bit RISC-V architecture. The “E” denotes the Embedded subset, with 16 general-purpose registers instead of the usual 32. The “C” indicates support for 16-bit compressed instructions, which improve code density.
Why does Dmitry Grinberg criticize RISC-V if he himself predicted it would win the cheap segment?
His objection isn’t that RISC-V will dominate that segment, but that he considers certain encoding decisions, like the offsets on compressed store instructions or Zicsr being a separate extension, avoidable design flaws, regardless of whether the end result works.
Can the CH32V003 replace any STM32 or ATtiny project?
Not in every case. Without a hardware multiplier or divider, tasks with intensive arithmetic, like signal processing or cryptography, perform worse than on a chip with those units. For simple control tasks, like reading sensors or driving digital outputs, it’s a valid and cheaper alternative.
What programmer is needed to flash the chip?
A WCH-LinkE adapter, which connects via the chip’s SWIO pin and costs just a few dollars. The same adapter also allows debugging with breakpoints.
Is there a fully open source toolchain for the CH32V003?
Yes. The ch32v003fun project offers examples, register definitions, and a build flow based on GCC for RISC-V, without relying on WCH’s proprietary IDE.
References
- rvembedded.com: the full reply from an embedded engineer in Trinidad and Tobago to Dmitry Grinberg’s article, published on August 16, 2026.
- dmitry.gr: Dmitry Grinberg’s site, author of “RISC-V: They Should Have Known Better,” the article that started the discussion.
- github.com/cnlohr/ch32v003fun: open source toolchain and examples for programming the CH32V003 without WCH’s proprietary IDE.
- riscv.org: official site of RISC-V International, the organization that maintains the architecture’s specifications.
- en.wikipedia.org/wiki/RISC-V: general reference on the RISC-V instruction set and its extensions.
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Imagen destacada: Foto de Mathew Schwartz en Unsplash
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